The hard part of AI chip supply is no longer only the fab. A large share of the delay now sits in advanced packaging, the step that turns separate dies and memory into a usable processor module.
That matters because even chips built in the US can still be sent to Taiwan for packaging before they go into servers. As AI demand rises, packaging capacity now affects delivery times, system design, and who gets access to the most advanced chips first.
Advanced packaging is now as important as the silicon
A modern AI chip is not one neat square of silicon. It is usually a package made from several parts, compute dies, stacks of high-bandwidth memory (HBM), an interposer or bridge, and a substrate that links the whole unit to the wider system.
For years, packaging sat in the background. It protected the chip, gave it pins or pads, and let it connect to a board. That old view no longer fits AI hardware. Today, packaging decides how many chiplets can work together, how close memory can sit to compute, and how much power the final module will consume.
That shift explains why a chip made in Arizona may still fly back to Taiwan before it ever reaches a US data centre. TSMC still performs almost all of its advanced packaging in Taiwan, even for wafers produced in the US. The packaging step has become a supply chain choke point because leading AI parts depend on it.
A few points make the issue clear:
- TSMC is preparing its first US advanced packaging plants near its Arizona fabs.
- Nvidia has reserved much of TSMC's leading CoWoS packaging capacity.
- Intel is the other large player in advanced packaging, with EMIB and Foveros work spread across Asia and the US.
- Samsung is also active in this space, with its own 2.5D and 3D approaches.
Three companies dominate the top end of both chip fabrication and advanced packaging: TSMC, Intel, and Samsung. That overlap is not an accident. Once chips move to chiplet-based design, the package becomes part of the performance story. A strong node without strong packaging is no longer enough.
What advanced packaging does inside an AI chip
Packaging has moved from protection to integration
A packaged chip still needs the basics. It must survive handling, testing, heat, and installation. However, the package now does much more than shield fragile silicon.
It also joins separate dies into one working product. That can mean combining logic built on one process node with memory built elsewhere, then bonding them onto the same package so they act like one device inside a server. The final module then connects to a circuit board, and from there into a blade or server assembly.
Paul Russo, who leads packaging solutions for TSMC in North America, described this change with a simple consumer analogy. Drinks did not change because the liquid improved alone. Bottles and cans changed how the product could be shipped, stored, and used. Chip packaging has followed a similar path. Protection still matters, but distribution and connection matter much more than they used to.
"It's the natural extension of Moore's law into the third dimension."
That line gets to the point. AI chips keep growing in size and power demand, but there are limits to making one monolithic die ever larger. Packaging allows firms to split the design into smaller dies, place them close together, and connect them at high speed.
How the process works
The steps are technical, but the core flow is easy to follow:
- Individual dies are "bumped" with microscopic metal connection points.
- Packaging tools then pick and place those dies onto a base layer, often a substrate or interposer.
- The package routes signals and power through multiple layers, often resin-based materials with copper wiring.
- The assembled part is protected, tested, and prepared for use in larger systems.
Those tiny bumps are the first connection points to the outside world. After that, placement accuracy matters because signal paths are short and dense. Any extra distance raises power use and can hurt performance.
The substrate is also doing heavy work. It is not a simple base plate. It carries power, routes data, and connects the final package to the circuit board. Intel is also investing in glass substrates because they can support finer features and tighter control for larger AI systems.
Meanwhile, demand has moved faster than supply. AI chip designers want more GPUs and more HBM inside a single package, but packaging plants were not built for this demand spike. The result is a shortage in the advanced steps, not only in the wafer fabs.
The packaging types shaping the AI race
The easiest way to see the shift is to compare the main packaging types side by side.
| Packaging type | Chip layout | Main use | Example technologies |
|---|---|---|---|
| 2D | One die mounted directly on substrate | CPUs, simpler devices, many standard parts | Flip-chip packaging |
| 2.5D | Multiple dies side by side, linked through an interposer or bridge | AI GPUs and large accelerators with HBM | TSMC CoWoS, Intel EMIB, Samsung iCube |
| 3D | Dies stacked on top of each other | Future logic stacks, advanced memory integration | TSMC SOIC, Intel Foveros Direct, Samsung XCube |
The key shift is simple. AI accelerators need much denser links than standard 2D packages can provide, so 2.5D and 3D methods are now moving to the centre of the market.
2D packaging still handles many chips
A large share of the chip market still uses 2D or flip-chip packaging. In this design, the die mounts directly onto the substrate. That works well for CPUs and many other parts where one die can do the job and memory does not need to sit inside the same advanced module.
This approach is cheaper and more mature. It also avoids some of the complexity of large interposers, bridges, and stacked dies. For standard workloads, that is enough.
AI training hardware has moved beyond that point. Large GPUs and custom accelerators need far more bandwidth between compute and memory, and that is where 2.5D packaging takes over.
2.5D packaging became the key step for GPUs
TSMC's best-known answer is CoWoS, short for chip-on-wafer-on-substrate. It first appeared in 2012 and is now tied closely to products from Nvidia, Google, Amazon, and MediaTek.
In CoWoS, the chips sit side by side, but a high-density interposer sits underneath them. That interposer acts as the missing "half" dimension. It gives the dies a much tighter communication path than a normal substrate alone can offer.
The benefit is clear with HBM. AI chips often hit a memory wall because the compute section cannot get enough data fast enough. By placing HBM close to the logic die, CoWoS gives the processor far more usable memory bandwidth.
TSMC has progressed through several CoWoS generations:
- CoWoS-S, with a large central silicon area and four HBM stacks around it
- CoWoS-R, a later version in the same family
- CoWoS-L, with two large silicon regions in the middle and up to 12 HBM stacks around them
CoWoS-L is the version linked to Nvidia Blackwell GPUs that started shipping last year. That matters because this is also the capacity that many firms worry about most. Nvidia has reportedly secured the majority of it, which tightens supply for rivals.
A recent report on TSMC and Intel packaging expansion highlighted how much CoWoS capacity has become tied to AI demand. When that step fills up, extra wafer output does not solve the problem on its own.
Intel EMIB takes a different route
Intel's 2.5D option is EMIB, or embedded multi-die interconnect bridge. Intel introduced it in 2017.
Instead of using a full interposer under the whole assembly, EMIB places small silicon bridges only where chips need to connect. That can reduce cost and material use because the package does not need one large silicon base beneath every die.
The design also works well for chiplet-based products with targeted high-speed links around the edges. Intel argues this approach saves time and allows smaller chipset sizes. Samsung's comparable 2.5D method is called iCube.
For teams tracking foundry options, this matters because EMIB gives Intel a packaging path that is distinct from TSMC's CoWoS. That can create another source of capacity when TSMC is full. Intel outlines its broader portfolio in its advanced packaging overview.
3D stacking is next, and hybrid bonding goes with it
The next step is true 3D packaging. Instead of laying chips side by side, 3D methods stack them on top of each other.
TSMC calls its version SOIC, system on integrated chips. Intel's is Foveros Direct. Samsung calls its approach XCube. The goal is the same across all three: reduce the distance between dies so they behave more like one chip.
That has a direct power benefit. Shorter paths use less energy. For data centres, that matters because power limits often cap how much compute operators can deploy in a rack or hall. Lower link power allows more useful silicon within the same power budget.
TSMC said products based on SOIC are still a couple of years away. Yet some 3D methods are already common in memory. Samsung, SK Hynix, and Micron stack memory dies into HBM today inside their own advanced packaging flows.
Hybrid bonding is part of that future. Instead of using metal bumps, it joins dies with near-flat copper pad-to-pad links. That reduces distance further and improves both power and electrical performance.
Why packaging capacity sits mostly in Asia
The geography of packaging has old roots. Packaging work moved to Asia in large part during the 1970s because it depended more on manual labour than front-end wafer fabrication did. Costs were lower, and the industry built up there over time.
Now the process is far more robotic, but the regional concentration remains. That creates a weak point for the AI supply chain. TSMC still performs all of its packaging in Taiwan at present, even for wafers made in Arizona. Intel also does much of its final packaging assembly in China, Vietnam, and Malaysia.
This concentration has become a national security issue as much as a supply issue. Tensions around Taiwan, plus wider instability in the region, create obvious risk for any product that depends on a cross-Pacific packaging loop.
For cloud buyers, researchers, and enterprise AI teams, the takeaway is simple. A chip can be "made in the US" at the wafer stage and still depend on Asia for the final step that turns it into a deployable accelerator.
The same point matters for timing. Shipping wafers out for packaging adds delay, transport risk, and coordination overhead. It also weakens the case for full domestic supply if the last key step stays offshore.
The US is building packaging capacity, but it will take time
TSMC is adding packaging near Arizona
TSMC plans to build its first two US advanced packaging plants near its Arizona fabs. That move should cut turnaround time because chips will no longer need to return to Taiwan for final assembly.
The company has not given a firm public timeline for volume output, but it has said it is moving as quickly as possible to meet customer demand. At the same time, TSMC is still ramping more packaging capacity in Taiwan.
Capacity growth is steep. TSMC said it is increasing CoWoS capacity at an 80% compound annual growth rate and SOIC capacity at a 100% compound annual growth rate. Those numbers show how hard the company is pushing the back end of the process, not only the fab.
Intel already has a partial US footprint
Intel has a more mixed model. Much of its final packaging still happens in Asia, but it also completes parts of EMIB and Foveros in the US, including New Mexico, Oregon, and Chandler, Arizona.
That Chandler site sits near Intel's 18A fab build-out. The close link between front-end and back-end work is important because packaging often becomes an entry point for foundry customers before they commit to full wafer production.
Gartner has said Intel has had packaging customers since 2022, including Amazon and Cisco. The report also said Elon Musk tapped Intel to package custom chips for SpaceX, xAI, and Tesla, while Nvidia has explored packaging work with Intel as part of its investment in the chipmaker.
In practice, that gives Intel a useful wedge. If a customer is unsure about moving front-end manufacturing, advanced packaging is a lower-risk first step.
OSATs are taking on more of the load
Smaller third-party providers, often called OSATs, also matter here. Amkor, which works with both TSMC and Intel, is building packaging capacity in Arizona. ASE, the world's largest OSAT, expects advanced packaging sales to double in 2026 and is building more CoWoS-related capacity in Taiwan.
That matters because almost every chip passes through an OSAT for at least part of the simpler finishing work. As demand rises, these firms are also taking on more advanced steps when major players cannot keep up alone.
What this bottleneck means for AI infrastructure buyers
For infrastructure teams, packaging is no longer a detail buried inside a component datasheet. It is part of the capacity equation for AI clusters, custom silicon programmes, and procurement plans.
If CoWoS capacity is booked, then more wafers do not automatically mean more deployable GPUs. If HBM integration is the limit, then the bottleneck sits in packaging rather than lithography. If a supplier lacks domestic packaging, then geography still shapes lead times and risk.
This also affects competition. TSMC says it wants to remain everyone's foundry, but heavy reservation of top-end packaging capacity by one buyer can still squeeze rivals. At the same time, Intel can use packaging to attract customers who are not ready to move entire designs onto its process technology.
For teams planning AI infrastructure across clouds, colocation, and on-prem estates, this is one more supply-side variable to track alongside GPU availability, rack power, and data location rules. If that discussion needs a deeper infra view, you can Book a Meeting with our Infra Experts to map how packaging constraints may affect deployment choices.
The main point is hard to ignore. The AI chip race is no longer decided only by who can etch the smallest features. It is also decided by who can package enough advanced parts, close enough to demand, and with enough memory beside the compute.
US-made wafers still crossing the Pacific for packaging show how incomplete domestic chip supply remains. Until more of that back-end capacity comes online, advanced packaging will stay one of the clearest limits on AI hardware growth.
That is why this issue reaches far beyond semiconductor engineering. It affects cloud capacity, national supply policy, and the pace at which new AI systems can reach real workloads.